1. Field of the Invention
The present invention relates to an improved method of providing an electrical power contact to an integrated circuit.
2. Description of the Prior Art
In order to provide an electrical power contact (e.g., V.sub.DD or V.sub.SS) to integrated circuits, a power conductor is routed around the "front" side of the chip; i.e, the side on which the field effect devices are formed. The power conductor connects the devices to a bondpad from which a wire lead connects to an integrated circuit package terminal, for connection to an external power supply. At least one power conductor, or "bus" is provided for each power supply voltage. To minimize inductance and resistance, usually several bonding pads are provided to connect a given bus with the package power supply terminals. For example, in one current microprocessor design, 15 V.sub.SS bondpads must be provided out of a total of 130 bondpads. In many cases the integrated circuit chips have now become "bondpad limited", with the periphery of the chip supporting the maximum number of bondpads possible. Hence, the large number of power supply bondpads reduce the number available for other purposes, such as signal inputs and outputs.
With high speed integrated circuits, an additional concern relates to electrical noise generated when output buffers turn on or off. Such switching noise voltages are due in part to the rapid change in current flow through the power supply conductors, which causes switching noise voltages to occur due to ohmic voltage drop across the resistance of the conductor, and to the inductive voltage produced by the inductance of the conductor. Such noise voltages can interfere with the other signals internal to the integrated circuit, or with the output signals from other output buffers. In particular, the change in current through the ground (V.sub.SS) power supply conductor causes "ground bounce" noise to be generated, wherein the internal ground potential bounces with respect to the external ground. The ground bounce noise is known to be caused in significant part by the switching of the output buffers, since they momentarily draw a relatively large current in order to charge up the capacitance of the external output lead to which they are connected. In some cases, a bus has been split into two or more portions connected to different areas of the integrated circuit, in an attempt to isolate the noise generated in one area from affecting devices in another area.
It is known to use conduction through a highly doped (e.g., low resistivity) substrate for making contact to a power supply. As discussed in U.S. Pat. No. 4,631,570, bipolar devices may be supplied with a positive power supply voltage (V.sub.CC) by a metallic contact on the back side of an integrated circuit chip. This allows contacting a buried collector region that is formed in an epitaxial layer on the substrate. However, the high resistivity of the epitaxial layer prevents the power supply voltage V.sub.CC from being supplied to devices located on the top surface (front) of the chip. For example, a resistor requires a separate surface contact thereto. This illustrates the fact that workers in the integrated circuit art have not considered it feasible to make a power supply contact from the backside of a chip through an epitaxial layer. This is due to the much higher resistivity (typically over an order of magnitude higher) of the epitaxial layer as compared to the substrate. It is also known to metallize the back side of an integrated circuit chip in order to provide a heat sink. For CMOS integrated circuits formed on a p+ substrate, the metal layer is typically connected to ground (V.sub.SS), in order to provide a bias that helps reduce latch-up. However, no significant current (i.e., no channel current) is intended to flow through this contact.
CMOS integrated circuits are frequently formed on semiconductor substrates that have an epitaxial layer. In most cases, the p and n channel devices are formed in doped "tub" regions located in the epitaxial layer. The epitaxial layer, formed by deposition onto a single crystal semiconductor wafer, is usually much less heavily doped than the wafer, with the tubs having a doping level intermediate between that of the wafer and the epitaxial layer. Hence, the epitaxial layer has a much higher resistivity than the wafer. This has led workers in the CMOS art to take great care to include a sufficient number of power supply bondpads on the front side of the chip to ensure that the above-noted "ground bounce" does not limit circuit performance. In practice, the number of V.sub.SS and V.sub.DD power supply bonding wires (and hence bondpads) is chosen based upon a calculation of the maximum inductance that can be tolerated for acceptable ground-bounce performance.